The present invention relates to an MOS switch circuit for transmitting an analog signal.
Recently, MOS switch circuits have been used in various types of circuits. FIG. 1 shows a circuit diagram of a conventional autozeroed comparator which includes an MOS switch circuit. The autozeroed comparator is described in "Monolithic Expandable 6 bit 20 MHz CMOS/SOS A/D Converter", Andrew G. F. Dingwall, IEEE J. Solid-State Circuits, Vol. SC-14, PP 926-932, December 1979 and is applied to an A/D converter. In the autozeroed comparator of the type described above, a reference signal end VR is connected to one end of a coupling capacitor 12 through an n-channel MOSFET 10 (as an MOS switch). A signal input end VI is also connected to one end of the coupling capacitor 12 through a p-channel MOSFET 14 (as an MOS switch). Clock pulses .phi. and .phi. are supplied to the gates of MOSFETs 10 and 14, respectively. The other end of the coupling capacitor 12 is connected to an output end OUT through a CMOS inverter 16. The CMOS inverter 16 comprises a p-channel MOSFET 18 which is connected to a power source VDD and an n-channel MOSFET 20 which is grounded. An n-channel MOSFET 22 (as an MOS switch) is connected in the input-output path of the CMOS inverter 16. The clock pulse .phi. is supplied to the gate of the n-channel MOSFET 22. The back gates of the MOSFETs 10 and 22 are grounded, whereas the back gate of the MOSFET 14 is connected to the power source VDD. In other words, the back gate voltages of the MOSFETs 10, 14 and 22 are constant.
In the comparator of the type described above, the MOSFETs 10 and 22 are ON for the duration of the clock pulse .phi.. At the same time, the reference voltage VR is supplied to one end of the coupling capacitor 12, and the CMOS inverter 16 is autozeroed to its toggle point. As a result, a potential difference between the reference voltage VR and the toggle voltage (=1/2 VDD) of the CMOS inverter 16 appears across the two ends of the capacitor 12. The MOSFETs 10 and 22 are OFF for the duration of the clock pulse .phi., whereas the MOSFET 14 is ON. Therefore, a voltage corresponding to a difference between the input voltage VI and the reference voltage VR is amplified by the CMOS inverter 16. An amplified voltage appears at the output end OUT. Since such an amplifier comprises only the CMOS inverter and MOS switches, it has a simple configuration and is suitable for circuit integration. As a result, the amplifier of this type is widely used as a basic circuit unit.
High speed operation is generally required for the A/D converter of the type described in the above reference. In order to achieve this end, the operating speed of the amplifier (as one of the slowest circuit elements) must be increased. More particularly, the time interval within which the MOSFET 22 of the amplifier is turned on and then the CMOS inverter 16 is completely autozeroed must be shortened. However, in the prior art, the single MOSFET 22 is used as an MOS switch, so that a ground voltage VSS (=0) is applied to the back gate. For this reason, when an input voltage of the CMOS inverter 16 is increased, a back gate bias effect occurs, thus increasing the ON resistance of the MOSFET 22. As a result, it takes a long time inverval for the CMOS inverter 16 to be autozeroed to its toggle point.
A channel width is conventionally increased to decrease the ON resistance of the MOSFET, even though this decreases the integrating density of the element. However, when the channel width of the MOSFET is increased, parasitic capacitances between the gate and source electrodes and between the gate and drain electrode are increased. As a result, the clock pulse .phi. leaks from the gate to the source and drain through the parasitic capacitances in accordance with a "field through" phenomenon, thereby increasing an offset voltage in the input-output path of the CMOS inverter 16. The offset voltage is one of the most important electrical characteristics, and preferably should not be increased. Therefore, it is preferred that the channel width (i.e., element size) of the MOSFET be smaller; thus an increase in channel width in favor of a decrease in ON resistance is not preferred in practice.
The ON resistance of a MOSFET is in proportion to a gate threshold voltage thereof. In general, an intrinsic MOS threshold voltage Vth.sub.o varies during various manufacturing processes. It is very difficult to keep the ON resistance at a constant small value. The gate threshold voltage of the MOSFET generally varies within a range of .+-.0.3 V. In particular, when the intrinsic MOS threshold voltage of the n-channel MOSFET is increased, the ON resistance thereof is greatly increased as compared with the p-channel MOSFET. FIG. 2 is a graph for explaining the ON resistance R.sub.on as a function of the input voltage (a voltage applied to the source or drain electrode) V.sub.in, using the intrinsic MOS threshold voltage Vth.sub.o as a parameter. FIG. 2 shows a case in which only a voltage of 5.0 V is applied to the gate electrode of the n-channel MOSFET in which W/L (the ratio of channel width W to channel length L) is 6/7 on the mask. Referring to FIG. 2, when the intrinsic MOS threshold voltage Vth.sub.o is 1.0 V, the ON resistance is 28 k.OMEGA.. When the intrinsic MOS threshold voltage Vth.sub.o is decreased by 0.3 V, the ON resistance is decreased to 19 k.OMEGA.. However, when the intrinsic MOS threshold voltage is increased by 0.3 V, the ON resistance is greatly increased to 65 k.OMEGA.. In short, when the intrinsic MOS threshold voltage Vth.sub.o is increased or decreased by the same voltage with respect to a given value, the ON resistance is increased more when the intrinsic MOS threshold voltage Vth.sub.o is increased than it is decreased when the intrinsic MOS threshold voltage Vth.sub.o is decreased.
As may be apparent from the above description, the conventional MOS switch circuit which uses MOSFETs fails to keep the ON resistance constant at a small value thereof. The variation in ON resistance also results in a disadvantage when an MOS switch circuit is used in place of the resistor in a switched-capacitor delay circuit. In other words, variation in ON resistance causes variation in delay time.